why larger tiling size need more on-chip memory

according to PowerVR Series5 Graphics.SGX architecture guide for developers.1.0.8.External.pdf: larger tilling size need more on-chip memory. But the different tile size just impacts the result (the intermediate buffer) in system memory, just wonder why it needs more on-chip memory? thanks.

A tile is processed entirely on chip. Enough memory has to be allocated on chip to accommodate the tile size, e.g. storing a 32-bit, colour, 24-bit depth and 8-bit stencil value per-pixel would require 64-bits of information (or, 8 bytes), which means for a 16x16 tile there would need to be 16x16x8=2048 bytes of storage on chip. Larger tile sizes would require more memory to be stored on chip for these operations.

got it, thanks.