from PowerVR Series5 Graphics.SGX architecture guide for developers.1.0.8.External.pdf:
the main advantage between Immediate Mode Rendering and Til Based Rendering is the on-chip color/depth/stencil buffer, so reduce the system memory bandwidth, and so the additional intermediate buffer is overweighed.
But I think the on-chip color/depth/stencil buffer could also be used by IMR, is this right? thanks.
Most modern IMR’s do have caches to improve performance, but the TBDR has an on-chip buffer that is big enough to store colour, depth and stencil data for an entire tile. This means all of these operations can be performed entirely on-chip.
Although there are some improvements in IMR’s when caching is used, depth and stencil information will have to be retrieved from system memory for each primitive that is processed, whereas the TBDR can do this all on chip. Additionally, the TBDR can do all blending on-chip using the colour buffer for the tile.
Having on-chip buffers also enables TBDR hardware to perform Hidden Surface Removal (HSR) for an entire tile, which significantly reduces overdraw to the point that an opaque only render will have no overdraw at all. The HSR process that the tiling enables is a key feature of the architecture that allows bandwidth to be lower than IMR’s, even when they are using early depth tests (for example, one of the major benefits is that the HSR in TBDR is inherently submission order independent for all objects, whereas IMR early depth tests are only optimal when an application submits all objects from front to back).Joe2011-08-02 11:08:58
Joe wrote:
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Having on-chip buffers also enables TBDR hardware to perform Hidden Surface Removal (HSR) for an entire tile, which significantly reduces overdraw to the point that an opaque only render will have no overdraw at all. The HSR process that the tiling enables is a key feature of the architecture that allows bandwidth to be lower than IMR's, even when they are using early depth tests (for example, one of the major benefits is that the HSR in TBDR is inherently submission order independent for all objects, whereas IMR early depth tests are only optimal when an application submits all objects from front to back).
Having on-chip buffers also enables TBDR hardware to perform Hidden Surface Removal (HSR) for an entire tile, which significantly reduces overdraw to the point that an opaque only render will have no overdraw at all. The HSR process that the tiling enables is a key feature of the architecture that allows bandwidth to be lower than IMR's, even when they are using early depth tests (for example, one of the major benefits is that the HSR in TBDR is inherently submission order independent for all objects, whereas IMR early depth tests are only optimal when an application submits all objects from front to back).
Regarding on "the HSR in TBDR is inherently submission order independent for all objects", what will happen if the depth test is disabled? My understanding on OpenGL and OpenGL ES spec is that the rendering result is submission order depedenet if depth test is disabled.
yjguo wrote:
Regarding on "the HSR in TBDR is inherently submission order independent for all objects", what will happen if the depth test is disabled? My understanding on OpenGL and OpenGL ES spec is that the rendering result is submission order depedenet if depth test is disabled.
The rendering result is submission order dependent and conformant with the OpenGL spec. However, with a non-deferred renderer performance is also submission order dependent, thus applications may have to sort the scene geometry front-to-back to get good performance. This is not necessary on a TBDR, since the HSR will remove hidden geometry even if it was rendered back-to-front.
thanks.
